Please respond if you are currently working on, or otherwise have an interest or stake in support for MMU-based platforms in Tock and paging support in particular. There are a couple parallel efforts underway, all of which would require careful consideration to achieve successfully alongside MPU-based protection. You can respond only to me (amit@amitlevy.com) but better to the list. For example, why you're interested (e.g. you have or are planning support for a platform that has an MMU, or there are specific features you'd hope to get from paging) and whether and what efforts you have underway. I will use this to ensure people are kept in the loop and included in discussions. Thanks! Amit
Amit Levy via Devel <devel@lists.tockos.org> writes:
Please respond if you are currently working on, or otherwise have an interest or stake in support for MMU-based platforms in Tock and paging support in particular.
I'd be interested in exploring the RISC-V side of this, for two reasons: - Given that at least one of the existing efforts [1] significantly touches the RISC-V arch crate---code that I have been maintaining in the past---I'd appreciate being kept in the loop. - I'm interested in MMU support for RISC-V more generally. My motivation comes from the fact that there are a number of RISC-V platforms with limited PMP implementations (due to its high impact on timing closures, e.g. [2]), but a full-featured and compliant MMU. MMU support go a long way for getting Tock working on these platforms in supervisor mode. That being said, I'm neither actively working on it, nor have any concrete project for which I'd be using this right now. Thanks! -Leon [1]: https://github.com/tock/tock/pull/4465 [2]: https://github.com/SpinalHDL/VexRiscv/pull/174
Hi, Am am interested in this, we are one of the groups implementing this for x86 now. Best regards. Alexandru
On 13 Jun 2025, at 17:42, Leon Schuermann via Devel <devel@lists.tockos.org> wrote:
Amit Levy via Devel <devel@lists.tockos.org> writes:
Please respond if you are currently working on, or otherwise have an interest or stake in support for MMU-based platforms in Tock and paging support in particular.
I'd be interested in exploring the RISC-V side of this, for two reasons:
- Given that at least one of the existing efforts [1] significantly touches the RISC-V arch crate---code that I have been maintaining in the past---I'd appreciate being kept in the loop.
- I'm interested in MMU support for RISC-V more generally. My motivation comes from the fact that there are a number of RISC-V platforms with limited PMP implementations (due to its high impact on timing closures, e.g. [2]), but a full-featured and compliant MMU. MMU support go a long way for getting Tock working on these platforms in supervisor mode. That being said, I'm neither actively working on it, nor have any concrete project for which I'd be using this right now.
Thanks!
-Leon
[1]: https://github.com/tock/tock/pull/4465 [2]: https://github.com/SpinalHDL/VexRiscv/pull/174 _______________________________________________ Devel mailing list -- devel@lists.tockos.org To unsubscribe send an email to devel-leave@lists.tockos.org
participants (3)
-
Alexandru Radovici -
Amit Levy -
Leon Schuermann